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1 a, low v in , low noise, cmos linear regulator data sheet adp1761 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features 1 a maximum output current low input voltage supply range v in = 1.10 v to 1.98 v, no external bias supply required fixed output voltage range: v out_fixed = 0.9 v to 1.5 v adjustable output voltage range: v out_adj = 0.5 v to 1.5 v ultralow noise: 2 v rms, 100 hz to 100 khz noise spectral density 4 nv/hz at 10 khz 3 nv/hz at 100 khz low dropout voltage: 30 mv typical at 1 a load operating supply current: 4.5 ma typical at no load 1.5% fixed output voltage accuracy over line, load, and temperature excellent power supply rejection ratio (psrr) performance 67 db typical at 10 khz at 1 a load 51 db typical at 100 khz at 1 a load excellent load/line transient response soft start to reduce inrush current optimized for small 10 f ceramic capacitors current-limit and thermal overload protection power-good indicator precision enable 16-lead, 3 mm 3 mm lfcsp package applications regulation to noise sensitive applications such as radio frequency (rf) transceivers, analog-to-digital converter (adc) and digital-to-analog converter (dac) circuits, phase-locked loops (plls), voltage controlled oscillators (vcos) and clocking integrated circuits field-programmable gate array (fpga) and digital signal processor (dsp) supplies medical and healthcare industrial and instrumentation general description the adp1761 is a low noise, low dropout (ldo) linear regulator. it is designed to operate from a single input supply with an input voltage as low as 1.10 v, without the requirement of an external bias supply to increase efficiency and provide up to 1 a of output current. the low 30 mv typical dropout voltage at a 1 a load allows the adp1761 to operate with a small headroom while maintaining regulation and providing better efficiency. typical application circuits vin en ss vreg vout sense c out 10f pg r pull-up 100k ? pg vadj gnd refcap c in 10f on off v out = 1.5v adp1761 v in = 1.7v c reg 1f c ref 1f c ss 10nf 12919-001 figure 1. fixed ou tput operation vin en ss vreg vout sense pg r pull-up 100k ? pg vadj gnd refcap c reg 1f c ref 1f r adj 10k ? c ss 10nf on off v out = 1.5v adp1761 v in = 1.7v c out 10f c in 10f 12919-002 figure 2. adjustable output operation table 1. related devices device input voltage maximum current fixed/ adjustable package adp1762 1.10 v to 1.98 v 2 a fixed/adjustable 16-lead lfcsp adp1763 1.10 v to 1.98 v 3 a fixed/adjustable 16-lead lfcsp adp1740 / adp1741 1.6 v to 3.6 v 2 a fixed/adjustable 16-lead lfcsp adp1752 / adp1753 1.6 v to 3.6 v 0.8 a fixed/adjustable 16-lead lfcsp adp1754 / adp1755 1.6 v to 3.6 v 1.2 a fixed/adjustable 16-lead lfcsp the adp1761 is optimized for stable operation with small 10 f ceramic output capacitors. the adp1761 delivers optimal transient performance with minimal board area. the adp1761 is available in fixed output voltages ranging from 0.9 v to 1.5 v. the output of the adjustable output model can be set from 0.5 v to 1.5 v through an external resistor connected between vadj and ground. the adp1761 has an externally programmable soft start time by connecting a capacitor to the ss pin. short-circuit and thermal overload protection circuits prevent damage in adverse conditions. the adp1761 is available in a small 16-lead lfcsp package for the smallest footprint solution to meet a variety of applications.
adp1761* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adp1761/adp1762/adp1763 evaluation board documentation data sheet ? adp1761: 1 a, low v in , low noise, cmos linear regulator data sheet user guides ? ug-954: evaluating the adp1761/adp1762/adp1763 low vin, low noise, cmos linear regulators tools and simulations ? adi linear regulator design tool and parametric search ? adisimpower? voltage regulator design tool reference materials press ? analog devices? low dropout regulators enable cleaner and faster communications design resources ? adp1761 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adp1761 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adp1761 data sheet rev. 0 | page 2 of 18 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical application circuits ............................................................ 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? input and output capacitor: recommended specifications.. 4 ? absolute maximum ratings ............................................................ 5 ? thermal data ................................................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 11 ? soft start function ..................................................................... 11 ? adjustable output voltage ........................................................ 12 ? enable feature ............................................................................ 12 ? power-good (pg) feature ........................................................ 12 ? applications information .............................................................. 13 ? capacitor selection .................................................................... 13 ? undervoltage lockout ............................................................... 14 ? current-limit and thermal overload protection ................. 14 ? thermal considerations ............................................................ 14 ? pcb layout considerations ...................................................... 17 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 4/16revision 0: initial version
data sheet adp1761 rev. 0 | page 3 of 18 specifications v in = v out + 0.2 v or v in = 1.1 v, whichever is greater, i load = 10 ma, c in = 10 f, c out = 10 f, c ref = 1 f, c reg = 1 f, t a = 25c, minimum and maximum limits at t j = ?40c to +125c, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ max unit input voltage supply range v in t j = ?40c to +125c 1.10 1.98 v current operating supply current i gnd i load = 0 a 4.5 8 ma i load = 10 ma 4.9 8 ma i load = 100 ma 5.5 8.5 ma i load = 1 a 7.3 11 ma shutdown current i gnd-sd en = gnd 2 a t j = ?40c to +85c, v in = (v out + 0.2 v) to 1.98 v 180 a t j = 85c to 125c, v in = (v out + 0.2 v) to 1.98 v 800 a output noise 1 out noise 10 hz to 100 khz, v in = 1.1 v, v out = 0.9 v 12 v rms 100 hz to 100 khz, v in = 1.1 v, v out = 0.9 v 2 v rms 10 hz to 100 khz, v in = 1.5 v, v out = 1.3 v 15 v rms 100 hz to 100 khz, v in = 1.5 v, v out = 1.3 v 2 v rms 10 hz to 100 khz, v in = 1.7 v, v out = 1.5 v 21 v rms 100 hz to 100 khz, v in = 1.7 v, v out = 1.5 v 2 v rms noise spectral density out nsd v out = 0.9 v to 1.5 v, i load = 100 ma at 10 khz 4 nv/hz at 100 khz 3 nv/hz power supply rejection ratio 1 psrr i load = 1 a, modulated v in 10 khz, v out = 1.3 v, v in = 1.5 v 67 db 100 khz, v out = 1.3 v, v in = 1.5 v 51 db 1 mhz, v out = 1.3 v, v in = 1.5 v 41 db 10 khz, v out = 0.9 v, v in = 1.1 v 66 db 100 khz, v out = 0.9 v, v in = 1.1 v 50 db 1 mhz, v out = 0.9 v, v in = 1.1 v 35 db output voltage output voltage range t a = 25c v out_fixed 0.9 1.5 v v out_adj 0.5 1.5 v fixed output voltage accuracy v out i load = 100 ma, t a = 25c ?0.5 +0.5 % 10 ma < i load < 1 a, v in = (v out + 0.2 v) to 1.98 v, t j = 0c to 85c ?1 +1.5 % 10 ma < i load < 1 a, v in = (v out + 0.2 v) to 1.98 v ?1.5 +1.5 % adjustable pin current i adj t a = 25c 49.5 50.0 50.5 a v in = (v out + 0.2 v) to 1.98 v 48.8 50.0 51.0 a adjustable output voltage gain factor a d t a = 25c 3.0 v in = (v out + 0.2 v) to 1.98 v 2.95 3.055 regulation line regulation ?v out /?v in v in = (v out + 0.2 v) to 1.98 v ?0.15 +0.15 %/v load regulation 2 ?v out /?i out i load = 10 ma to 1 a 0.25 0.44 %/a dropout voltage 3 v dropout i load = 100 ma, v out = 1.2 v 12 23 mv i load = 1 a, v out = 1.2 v 30 53 mv start-up time 1, 4 t start-up c ss = 10 nf, v out = 1.3 v 0.6 ms soft start current i ss 1.1 v v in 1.98 v 8 10 12 a current-limit threshold 5 i limit 1.5 2 2.4 a
adp1761 data sheet rev. 0 | page 4 of 18 parameter symbol test conditions/comments min typ max unit thermal shutdown threshold ts sd t j rising 150 c hysteresis ts sd-hys 15 c power-good (pg) output threshold output voltage falling pg fall 1.1 v v in 1.98 v ?7.5 % rising pg rise 1.1 v v in 1.98 v ?5 % pg output output voltage low pg low 1.1 v v in 1.98 v, i pg 1 ma 0.35 v leakage current i pg-lkg 1.1 v v in 1.98 v 0.01 1 a delay 1 pg delay en rising to pg rising 0.75 ms precision en input 1.1 v v in 1.98 v logic input high en high 595 625 690 mv low en low 550 580 630 mv input logic hysteresis en hys 45 mv input leakage current i en-lkg en = v in or gnd 0.01 1 a input delay time ti en-dly from en rising from 0 v to v in to 0.1 v out 100 s undervoltage lockout uvlo input voltage rising uvlo rise t j = ?40c to +125c 1.01 1.06 v falling uvlo fall t j = ?40c to +125c 0.87 0.93 v hysteresis uvlo hys 90 mv 1 guaranteed by design and characterization; not production tested. 2 based on an endpoint calculation using 10 ma and 1 a loads. 3 dropout voltage is defined as the input to output voltage differ ential when the input voltage is set to the nominal output vol tage, which applies only for output voltages above 1.1 v. 4 start-up time is defined as the time from the rising edge of en to vout being at 90% of its nominal value. 5 current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 1.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 1.0 v, or 0.9 v. input and output capacitor: recommended specifications table 3. parameter symbol test conditions/comments min typ max unit capacitance 1 t a = ?40c to +125c input c in 7.0 10 f output c out 7.0 10 f regulator c reg 0.7 1 f reference c ref 0.7 1 f capacitor equivalent series resistance (esr) r esr t a = ?40c to +125c c in , c out 0.001 0.5 c reg , c ref 0.001 0.2 1 the minimum input and output capacitance must be >7.0 f over the full range of the operating conditions. consider the full ra nge of the operating conditions in the application during device selection to en sure that the minimum capacitance specification is met. x7r and x5r type capacitors ar e recommended. y5v and z5u capacitors are not recommended for use with any ldo.
data sheet adp1761 rev. 0 | page 5 of 18 absolute maximum ratings table 4. parameter rating vin to gnd ?0.3 v to +2.16 v en to gnd ?0.3 v to +3.96 v vout to gnd ?0.3 v to vin sense to gnd ?0.3 v to vin vreg to gnd ?0.3 v to vin refcap to gnd ?0.3 v to vin vadj to gnd ?0.3 v to vin ss to gnd ?0.3 v to vin pg to gnd ?0.3 v to +3.96 v storage temperature range ?65c to +150c operating temperature range ?40c to +125c operating junction temperature 125c lead temperature (soldering, 10 sec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal data absolute maximum ratings apply only individually, not in combination. the adp1761 may be damaged when junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temper- ature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction to ambient thermal resistance of the package ( ja ). t j is calculated using the following formula: t j = t a + ( p d ja ) the junction to ambient thermal resistance ( ja ) of the package is based on modeling and a calculation using a 4-layer board. the junction to ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in 3 in circuit board. for details about board construction, refer to jedec jesd51-7. jb is the junction to board thermal characterization parameter with units of c/w. jb of the package is based on modeling and a calculation using a 4-layer board. the jedec jesd51-12 document, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path, as in thermal resistance ( jb ). therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. the maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ), using the following formula: t j = t b + ( p d jb ) refer to the jedec jesd51-8 and jesd51-12 documents for more detailed information about jb . thermal resistance ja and jb are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance for a 4-layer 6400 mm 2 copper size package type ja jb unit 16-lead lfcsp 56 28.4 c/w esd caution
adp1761 data sheet rev. 0 | page 6 of 18 pin configuration and fu nction descriptions 12 11 10 1 3 49 2 6 5 7 8 1 6 1 5 1 4 1 3 vin vin vin vin vout notes 1. the exposed pad is electrically connected to gnd. it is recommended that this pad be connected to a ground plane on the pcb. the exposed pad is on the bottom of the package. sense ss pg en vout vout vout refcap vreg gnd vadj adp1761 top view (not to scale) 12919-003 figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 to 4 vin regulator input supply. bypass vin to gnd with a 10 f or gr eater capacitor. note that all four vin pins must be connected to the source supply. 5 refcap reference filter capacitor. connect a 1 f capacitor from the refcap pin to ground. do not connect a load to ground. 6 vreg regulated input supply to ldo amplifier. bypass vreg to gnd with a 1 f or greater capacitor. do not connect a load to ground. 7 gnd ground. 8 vadj adjustable voltage pin for the adjustable output option. connect a 10 k external resistor between the vadj pin and ground to set the output voltage to 1.5 v. for the fixed output option, leave this pin floating. 9 to 12 vout regulated output voltage. bypass vout to gnd with a 10 f or greater capacitor. note that all four vout pins must be connected to the load. 13 sense sense input. the sense pin measures the actual output volt age at the load and feeds it to the error amplifier. connect vsense as close to the load as possible to minimize the effect of ir voltage drop between vout and the load. 14 ss soft start pin. a 10 nf capacitor connected to the ss pin and ground sets the start-up time to 0.6 ms. 15 pg power-good output. this open-drain output requires an exte rnal pull-up resistor. if the device is in shutdown mode, current-limit mode, or thermal shutdown mode , or if vout falls below 90% of the nominal output voltage, the pg pin immediately transitions low. 16 en enable input. drive the en pin high to turn on the regulator. drive the en pin low to turn off the regulator. for automatic startup, connect the en pin to the vin pin. ep exposed pad. the exposed pad is electrically connected to gnd. it is recommended that this pad be connected to a ground plane on the pcb. the exposed pad is on the bottom of the package.
data sheet adp1761 rev. 0 | page 7 of 18 typical performance characteristics v in = 1.5 v, v out = 1.3 v, t a = 25c, unless otherwise noted. 12919-004 output voltage (v) junction temperature (c) 1.295 1.297 1.299 1.301 1.303 1.305 ?50 ?25 0 25 50 75 100 125 150 no load i load = 10ma i load = 100ma i load = 1a figure 4. output voltage (v out ) vs. junction temperature 12919-005 1.3015 1.3020 1.3025 1.3030 1.3035 0.01 0.1 1 output voltage (v) load current (a) figure 5. output voltage (v out ) vs. load current 12919-006 1.298 1.300 1.302 1.304 1.306 1.308 1.310 1.51.61.71.81.92.0 output vol t age (v) input voltage (v) i load = 100ma i load = 500ma i load = 1a figure 6. output voltage vs. input voltage 0 1 2 3 4 5 6 7 8 9 10 ?50 ?25 0 25 50 75 100 125 150 ground current (ma) junction temperature (c) no load i load = 10ma i load = 100ma i load = 200ma i load = 500ma i load = 1a 12919-007 figure 7. ground current vs. junction temperature 0 1 2 3 4 5 6 7 8 0.01 0.1 1 ground current (ma) load current (a) 12919-008 figure 8. ground current vs. load current 0 1 2 3 4 5 6 7 8 9 1.5 1.6 1.7 1.8 1.9 2.0 ground current (ma) input voltage (v) no load i load = 10ma i load = 100ma i load = 200ma i load = 500ma i load = 1a 12919-009 figure 9. ground current vs. input voltage
adp1761 data sheet rev. 0 | page 8 of 18 ?20 0 20 40 60 80 100 120 140 160 180 200 ?50 ?25 0 25 50 75 100 125 150 shutdown current (a) junction temperature (c) v in = 1.5v v in = 1.7v v in = 1.9v v in = 1.6v v in = 1.8v v in = 1.98v 12919-010 figure 10. shutdown current vs. junction temperature at various input voltages (v in ) 12919-011 0 5 10 15 20 25 30 35 0.1 1 dropout vol t age (mv) load (a) figure 11. dropout voltage vs. load current, v out = 1.3 v 12919-012 1.10 1.15 1.20 1.25 1.30 1.35 1.2 1.3 1.4 1.5 output voltage (v) input voltage (v) i load = 100ma i load = 500ma i load = 1a figure 12. output voltage vs. input voltage (in dropout), v out = 1.3 v 0 1 2 3 4 5 6 7 8 9 1.11.21.31.41.51.6 ground current (ma) input voltage (v) no load i load = 10ma i load = 100ma i load = 200ma i load = 500ma i load = 1a 12919-013 figure 13. ground current vs. input voltage (in dropout), v out = 1.3 v ch1 20.0mv ch2 500ma m4.00s a ch2 640ma 1 2 t 18.70% v out i load 3a/s slew rate 12919-014 figure 14. load transient response, c out = 10 f, v in = 1.7 v, v out = 1.3 v ch1 20.0mv ch2 500ma m4.00s a ch2 640ma 2 1 t 19.00% v in i load 3a/s slew rate 12919-015 figure 15. load transient response, c out = 47 f, v in = 1.7 v, v out = 1.3 v
data sheet adp1761 rev. 0 | page 9 of 18 ch1 5.00mv ch2 500mv m2.00s a ch2 1.68v 2 1 t 17.50% v out v in 1v/s slew rate 12919-016 figure 16. line transient resp onse, load current = 1 a, v in = 1.5 v to 1.98 v step, v out = 1.3 v 0 2 4 6 8 10 12 14 16 0.1 1 noise (v rms) load current (a) v out = 1.3v (100hz to 100khz) v out = 1.3v (10hz to 100khz) 12919-017 figure 17. noise vs. load current for various output voltages 0.1 1 10 100 1k 10k 10 100 1k 10k 100k noise spectral density (nv/ hz) frequency (hz) v out = 0.9v v out = 1.3v v out = 1.5v 12919-018 figure 18. noise spectral density vs. fr equency for various output voltages, load current = 100 ma 12919-019 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ? 10 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) v in = 1.1v v in = 1.2v v in = 1.3v v in = 1.4v v in = 1.5v v in = 1.6v figure 19. power supply rejection rati o (psrr) vs. frequency for various v in , v out = 0.9 v, load current = 1 a 12919-020 1 10 100 1k 10k 100k 1m 10m ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ? 10 psrr (db) frequency (hz) v in = 1.5v v in = 1.6v v in = 1.7v v in = 1.8v v in = 1.9v v in = 1.98v figure 20. power supply rejection ratio (psrr) vs. frequency for various v in , v out = 1.3 v, load current = 1 a 12919-021 1 10 100 1k 10k 100k 1m 10m ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ? 10 psrr (db) frequency (hz) v in = 1.7v v in = 1.8v v in = 1.9v v in = 1.98v figure 21. power supply rejection rati o (psrr) vs. frequency for various v in , v out = 1.5 v, load current = 1 a
adp1761 data sheet rev. 0 | page 10 of 18 12919-022 1 10 100 1k 10k 100k 1m 10m ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ? 10 psrr (db) frequency (hz) i load = 100ma i load = 200ma i load = 500ma i load = 1a figure 22. power supply rejection ratio (psrr) vs. frequency for various loads, v out = 1.3 v, v in = 1.5 v
data sheet adp1761 rev. 0 | page 11 of 18 theory of operation the adp1761 is an ldo, low noise linear regulator that uses an advanced proprietary architecture to achieve high efficiency regulation. it also provides high psrr and excellent line and load transient response using a small 10 ? f ceramic output capacitor. the device operates from a 1.10 v to 1.98 v input rail to provide up to 1 a of output current. supply current in shutdown mode is 2 a. ss block refcap ss pg short-circuit, thermal project internal bias supply adp1761 vin vreg en gnd reference, bias vout sense 12919-023 figure 23. functional block diagram, fixed output ss block short-circuit, thermal project internal bias supply refcap ss pg vin v re g vadj i adj en gnd vout sense adp1761 12919-024 figure 24. functional block diagram, adjustable output internally, the adp1761 consists of a reference, an error amplifier, and a pass device. the output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system that ideally drives the feedback voltage to equal the reference voltage. if the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. if the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. the adp1761 is available in output voltages ranging from 0.9 v to 1.5 v for a fixed output. contact a local analog devices, inc., sales representative for other fixed voltage options. the adjustable output option can be set from 0.5 v to 1.5 v. the adp1761 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on. when en is low, vout turns off. for automatic startup, tie en to vin. soft start function for applications that require a controlled startup, the adp1761 provides a programmable soft start function. the programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. to implement soft start, connect a small ceramic capacitor from ss to ground. at startup, a 10 a current source charges this capacitor. the voltage at ss limits the adp1761 start-up output voltage, providing a smooth ramp-up to the nominal output voltage. to calculate the start-up time for the fixed output and adjustable output, use the following equations: t start-up_fixed = t delay + v ref ( c ss / i ss ) (1) t start-up_adj = t delay + v adj ( c ss / i ss ) (2) where: t delay is a fixed delay of 100 s. v ref is a 0.5 v internal reference for the fixed output model option. c ss is the soft start capacitance from ss to gnd. i ss is the current sourced from ss (10 a). v adj is the voltage at the vadj pin equal to r adj i adj . time (ms) v out, en (v) ?0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 ?0.2 0.3 0.8 1.3 1.8 en c ss = 0nf c ss = 10nf c ss = 22nf 12919-025 figure 25. fixed v out ramp-up with external soft start capacitor (v out, en ) vs. time ?0.5 0 0.5 1.0 1.5 2.0 ?0.2 0.3 0.8 1.3 1.8 v out, en (v) time (ms) en v out = 0.5v; c ss = 10nf v out = 0.5v; c ss = 22nf v out = 1.5v; c ss = 10nf v out = 1.5v; c ss = 22nf 12919-226 figure 26. adjustable v out ramp-up with external soft start capacitor (v out, en ) vs. time
adp1761 data sheet rev. 0 | page 12 of 18 adjustable output voltage the output voltage of the adp1761 can be set over a 0.5 v to 1.5 v range. connect a resistor (r adj ) from the vadj pin to ground to set the output voltage. to calculate the output voltage, use the following equation: v out = a d ( r adj i adj ) (3) where: a d is the gain factor with a typical value of 3.0 between the vadj pin and the vout pin. i adj is the 50.0 a constant current out of the vadj pin. enable feature the adp1761 uses the en pin to enable and disable the vout pins under normal operating conditions. as shown in figure 27, when a rising voltage on en crosses the active threshold, vout turns on. when a falling voltage on en crosses the inactive threshold, vout turns off. ch1 200mv ch2 200mv m4.0ms a ch1 768mv 1 t 8.26ms en v out 12919-026 b w b w figure 27. typical en pin operation as shown in figure 28, the en pin has hysteresis built in. this hysteresis prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 en voltage (v) 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 output vol t age (v) 12919-127 figure 28. output voltage vs. typical en pin voltage, v out = 1.3 v power-good (pg) feature the adp1761 provides a power-good pin (pg) to indicate the status of the output. this open-drain output requires an external pull-up resistor that can be connected to v in or v out . if the device is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, pg immediately transitions low. during soft start, the rising threshold of the power-good signal is 95% of the nominal output voltage. the open-drain output is held low when the adp1761 has a sufficient input voltage to turn on the internal pg transistor. an optional soft start delay can be detected. the pg transistor is terminated via a pull-up resistor to v out or v in . power-good accuracy is 92.5% of the nominal regulator output voltage when this voltage is rising, with a 95% trip point when this voltage is falling. regulator input voltage brownouts or glitches trigger a power no good if v out falls below 92.5%. a normal power-down triggers a power good when v out is at 95%. ch1 1.00v ch2 1.00v m100s a ch4 420mv 1 2 4 t 228.0000s ch4 1.00v v in v out pg 12919-027 figure 29. typical pg behavior vs. v out , v in rising (v out = 1.3 v) 1 2 4 ch1 1.00v ch2 1.00v m200s a ch1 3.00v t 0.000000s ch4 1.00v v in v out pg 12919-128 figure 30. typical pg behavior vs. v out , v in falling (v out = 1.3 v)
data sheet adp1761 rev. 0 | page 13 of 18 applications information capacitor selection output capacitor the adp1761 is designed for operation with small, space-saving ceramic capacitors, but it can function with most commonly used capacitors as long as care is taken with the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 10 f capacitance with an esr of 500 m or less is recommended to ensure the stability of the adp1761 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp1761 to large changes in load current. figure 31 and figure 32 show the transient responses for output capacitance values of 10 f and 47 f, respectively. ch1 20.0mv ch2 500ma m1.00s a ch2 640ma 1 2 t 18.70% 12919-030 v out i load b w figure 31. output transient response, c out = 10 f ch1 20.0mv ch2 500ma m1.00s a ch2 640ma 1 2 t 19.00% 12919-031 v in i load figure 32. output transient response, c out = 47 f input bypass capacitor connecting a 10 f capacitor from the vin pin to the gnd pin to ground reduces the circuit sensitivity to the pcb layout, especially when long input traces or a high source impedance is encountered. if output capacitance greater than 10 f is required, it is recommended that the input capacitor be increased to match it. input and output capacitor properties use any good quality ceramic capacitors with the adp1761 , as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. figure 33 shows the capacitance vs. bias voltage characteristics of an 0805 case, 10 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c temperature range and is not a function of package size or voltage rating. 0 2 4 6 8 10 12 0123456 dc bias voltage (v) c a pacitance (f) 12919-032 figure 33. capacitance vs. dc bias voltage use equation 4 to determine the worst case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c out (1 ? tempco ) (1 ? tol) (4) where: c eff is the effective capacitance at the operating voltage. c out is the output capacitor. tempco is the worst case capacitor temperature coefficient. tol is the worst case component tolerance. in this example, the worst case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out = 10 f at 1.0 v, as shown in figure 33. substituting these values in equation 4 yields c eff = 10 f (1 ? 0.15) (1 ? 0.1) = 7.65 f
adp1761 data sheet rev. 0 | page 14 of 18 therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp1761 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. undervoltage lockout the adp1761 has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 1.06 v. the uvlo ensures that the adp1761 inputs and the output behave in a predictable manner during power-up. current-limit and thermal overload protection the adp1761 is protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. the adp1761 is designed to reach the current limit when the output load reaches 2 a (typical). when the output load exceeds 2 a, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature drops below 135c (typical), the output is turned on again, and the output current is restored to its nominal value. consider the case where a hard short from vout to ground occurs. at first, the adp1761 reaches the current limit so that only 2 a is conducted into the short circuit. if self-heating of the junction becomes great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 2 a into the short circuit, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 2 a and 0 a that continues as long as the short circuit remains at the output. current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. for reliable operation, limit the device power dissipation externally so that junction temperatures do not exceed 125c. thermal considerations to guarantee reliable operation, the junction temperature of the adp1761 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistance between the junction and ambient air ( ja ). the ja value is dependent on the package assembly compounds used and the amount of copper to which the gnd pin and the exposed pad (epad) of the package are soldered on the pcb. table 7 shows typical ja values for the 16-lead lfcsp for various pcb copper sizes. table 8 shows typical jb values for the 16-lead lfcsp. table 7. typical ja values copper size (mm 2 ) ja (c/w), lfcsp 25 138.1 100 102.9 500 76.9 1000 67.3 6400 56 table 8. typical jb values copper size (mm 2 ) jb (c/w) at 1 w 100 33.3 500 28.9 1000 28.5 to calculate the junction temperature of the adp1761 , use the following equation: t j = t a + ( p d ja ) (5) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = (( v in ? v out ) i load ) + ( v in i gnd ) (6) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. as shown in equation 6, for a given ambient temperature and computed power dissipation, a minimum copper size requirement exists for the pcb to ensure that the junction temperature does not rise above 125c.
data sheet adp1761 rev. 0 | page 15 of 18 figure 34 through figure 39 show the junction temperature calculations for the different ambient temperatures, load currents, v in to v out differentials, and areas of pcb copper. 0 20 40 60 80 100 120 140 0.20.40.60.81.01.21.41.6 junction temper a ture (c) v in ? v out (v) t j max 10ma 100ma 500ma 1a 12919-034 figure 34. 6400 mm 2 of pcb copper, t a = 25c v in ? v out (v) 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-035 figure 35. 500 mm 2 of pcb copper, t a = 25c v in ? v out (v) 0 20 40 60 80 100 120 140 0.20.40.60.81.01.21.41.6 junction tempe r a ture (c) 10ma 100ma 500ma 1a t j max 12919-036 figure 36. 25 mm 2 of pcb copper, t a = 25c v in ? v out (v) 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-037 figure 37. 6400 mm 2 of pcb copper, t a = 50c v in ? v out (v) 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-038 figure 38. 500 mm 2 of pcb copper, t a = 50c v in ? v out (v) 0 20 40 60 80 100 120 140 0.20.40.60.81.01.21.41.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-039 figure 39. 25 mm 2 of pcb copper, t a = 50c
adp1761 data sheet rev. 0 | page 16 of 18 in cases where the board temperature is known, the thermal characterization parameter ( jb ) can be used to estimate the junction temperature rise. the maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (7) figure 40 through figure 43 show the junction temperature calculations for the different board temperatures, load currents, v in to v out differentials, and areas of pcb copper. v in ? v out (v) 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 junction tempe r a ture (c) 10ma 100ma 500ma 1a t j max 12919-040 figure 40. 500 mm 2 of pcb copper, t b = 25c 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-041 v in ? v out (v) figure 41. 500 mm 2 of pcb copper, t b = 50c v in ? v out (v) 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-042 figure 42. 1000 mm 2 of pcb copper, t b = 25c v in ? v out (v) 0 20 40 60 80 100 120 140 0.20.40.60.81.01.21.41.6 junction temper a ture (c) 10ma 100ma 500ma 1a t j max 12919-043 figure 43. 1000 mm 2 of pcb copper, t b = 50c
data sheet adp1761 rev. 0 | page 17 of 18 pcb layout considerations heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp1761 . however, as shown in table 8, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. use the following recommendations when designing pcbs: ? place the input capacitor as close as possible to the vin and gnd pins. ? place the output capacitor as close as possible to the vout and gnd pins. ? place the soft start capacitor (c ss ) as close as possible to the ss pin. ? place the reference capacitor (c ref ) and regulator capacitor (c reg ) as close as possible to the refcap pin and the vreg pin, respectively. ? connect the load as close as possible to the vout and sense pins. use of 0603 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. 12919-044 figure 44. evaluation board 12919-045 figure 45. typical board layout, top side 12919-046 figure 46. typical board layout, bottom side
adp1761 data sheet rev. 0 | page 18 of 18 outline dimensions 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indi c ator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 47. 16-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp-16-22) dimensions shown in millimeters ordering guide model 1 temperature range output voltage (v) 2 package description package option branding adp1761acpz-r7 ?40c to +125c adjustable 16-lead le ad frame chip scale package [lfcsp] cp-16-22 lrj adp1761acpz-0.9-r7 ?40c to +125c 0.9 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrk adp1761acpz0.95-r7 ?40c to +125c 0.95 16-lead lead frame chip scale package [lfcsp] cp-16-22 lun adp1761acpz-1.0-r7 ?40c to +125c 1.0 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrl adp1761acpz-1.1-r7 ?40c to +125c 1.1 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrm adp1761acpz-1.2-r7 ?40c to +125c 1.2 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrn adp1761acpz1.25-r7 ?40c to +125c 1.25 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrp adp1761acpz-1.3-r7 ?40c to +125c 1.3 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrq adp1761acpz-1.5-r7 ?40c to +125c 1.5 16-lead lead frame chip scale package [lfcsp] cp-16-22 lrr adp1761-1.3-evalz 1.3 evaluation board adp1761-adj-evalz 1.1 evaluation board 1 z = rohs compliant part. 2 for additional options, contact a local analog devices sales or distribution representative. additional voltage output options available include the following: 0.5 v, 0.55 v, 0.6 v, 0.65 v, 0.7 v, 0.75 v, 0.8 v, 0.85 v, 1.05 v, 1.15 v, 1.35 v, 1.4 v, or 1.45 v. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12919-0-4/16(0)

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